`include "defines.v"
module pc_reg(
	input wire clk,
	input wire rst,
	output reg[31:0] pc,
	output reg ce
);
	always@(posedge clk)
		if(rst == `RstEnable) begin
			ce <= `ChipDisable;
			end
		else begin
			ce <= `ChipEnable;
			end
	always@(posedge clk)
		if(ce == `ChipEnable)
			pc <= pc + 4;
		else
			pc <= 0;
endmodule
